![]() ![]() Be sure to correct your design before synthesizing the circuit to the Spartan-3E FPGA board. Due to the memory limitations of the computers within the ECE 274 Laboratory, you should test your design assuming a refresh period is 16 us (instead of 16 ms). Create a testbench to test the Multiplexed BCD Display Driver for correct functionality for one full refresh period.Note: You will need to accurately describe how your Refresher component works to your TA to receive full points. The Multiplexed BCD Display Driver should be modeled structurally, but the Refresher sub-component can be modeled behaviorally. Design the Multiplexed BCD Display Driver and Refresher sub-components.No specific requirements are needed for the testbench, but you must be able to demonstrate the correctness of your design to your TA. Create a testbench to test the Binary to BCD Converter for correct functionality.Note: If you choose to model the entire Binary to BCD Converter behaviorally as one Verilog module, you will receive a maximum of 25 points. Note that you do not need to utilize all components listed above, but rather you are restricted to those components. Each datapath component used must be modeled behaviorally as a separate Verilog module, and the Binary to BCD Converter must be implemented as a structural connection of those datapath components. Structurally design the Binary to BCD Converter using any of the following datapath components: adders, subtractors, incrementers, decrementers, multipliers, comparators, shifters, registers, multiplexers, decoders, encoders, and logic gates (only when necessary).The following provides an overview of the multiplexed BCD to 7-segment display driver. The Multiplexed BCD Display Driver builds upon your binary to 7-segment decoder by adding a refresher circuit to control when each 7-segment display will be illuminated and a multiplexer to select between the Tens and Ones output of the Binary to BCD Converter. In this lab, you will also design and build a Multiplexed BCD Display Driver to display the Tens and Ones outputs of the Binary to BCD Converter on the corresponding 7-segment LED displays. Instead, by repeatedly and continuously display a digit on each display faster than the human eye can respond, both displays will appear to be illuminated at the same time. As such, we cannot simultaneously display a digit on both 7-segment LED displays. In designing the binary to 7-segment LED decoder in Lab 2, the SegSel output was used to control which 7-segment LED display would be utilized to display the 4-bit binary number. Multiplexed 2-digit BCD Display Controller ![]()
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